EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 368

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Configuration Features
11–8
Stratix III Device Handbook, Volume 1
f
Design Security Using Configuration Bitstream Encryption
Stratix III devices support decryption of configuration bitstream using
the advanced encryption standard (AES) algorithm—the most advanced
encryption algorithm available today. Both non-volatile and volatile key
programming are supported using Stratix III devices. When using the
design security feature, a 256-bit security key is stored in the Stratix III
device. In order to successfully configure a Stratix III device that has the
design security feature enabled, it must be configured with a
configuration file that was encrypted using the same 256-bit security key.
Non-volatile key programming does not require any external devices,
such as a battery backup, for storage. However, for different applications,
you can store the security keys in volatile memory in the Stratix III device.
An external battery is needed for this volatile key storage.
1
1
Remote System Upgrade
Stratix III devices feature remote update. For more information about
this feature, refer to the
volume 1 of the Stratix III Device Handbook.
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply
voltage levels have stabilized on power-up. Upon power-up, the device
does not release nSTATUS until V
the device's POR trip point. On power down, brown-out will occur if V
or V
or V
In Stratix III devices, a pin-selectable option (PORSEL) is provided that
allows you to select between a typical POR time setting of 12 ms or
100 ms. In both cases, you can extend the POR time by using an external
component to assert the nSTATUS pin low.
CCL
CCPGM
ramps down below the POR trip point and any of the V
When using a serial configuration scheme such as PS or fast AS,
configuration time is the same whether or not the design
security feature is enabled. If the FPP scheme is used with the
design security or decompression feature, a ×4 DCLK is required.
This results in a slower configuration time when compared to
the configuration time of a Stratix III device that has neither the
design security, nor the decompression feature enabled.
For more information about this feature, refer to the
Security in Stratix III Devices
Device Handbook.
drops below the threshold voltage.
Remote System Upgrades with Stratix III Devices
CCL
chapter in volume 1 of the Stratix III
, V
CC
, V
CCPD
, and V
Altera Corporation
CCPGM
November 2007
Design
are above
CC
, V
CCPD,
CC
in