EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 441

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
TMS
TCK
TRST
Table 13–1. IEEE Std. 1149.1 Pin Descriptions (Part 2 of 2)
Pin
Test mode select
Test clock input
Test reset input
(optional)
Description
The IEEE Std. 1149.1 BST circuitry requires the following registers:
■
■
■
Figure 13–2
The instruction register determines the action to be performed and
the data register to be accessed.
The bypass register is a one-bit-long data register that provides a
minimum-length serial path between TDI and TDO.
The boundary-scan register is a shift register composed of all the
boundary-scan cells of the device.
Input pin that provides the control signal to determine the transitions of
the test access port (TAP) controller state machine. Transitions within
the state machine occur at the rising edge of
set up
rising edge of
you drive
The clock input to the BST circuitry. Some operations occur at the
rising edge, while others occur at the falling edge.
Active-low input to asynchronously reset the boundary-scan circuit.
You should drive this pin low when not in boundary-scan operation.
For non-JTAG users, you should permanently tie the pin to GND.
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
shows a functional model of the IEEE Std. 1149.1 circuitry.
TMS
TMS
before the rising edge of
TCK
high.
. During non-JTAG operation, Altera
Stratix III Device Handbook, Volume 1
Function
TCK
.
TMS
TCK
is evaluated on the
. Therefore, you must
®
recommends
13–3