EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 358

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Power-On Reset Specifications
Power-On Reset
Specifications
10–6
Stratix III Device Handbook, Volume 1
The POR circuit monitors the power supplies listed in
The POR circuit does not monitor the power supplies listed in
The POR specification is designed to ensure that all the circuits in the
Stratix III device are at certain known states during power up.
The POR signal pulse width is programmable using the PORSEL input
pin. When PORSEL is set to low, the POR signal pulse width is set to
100 ms. A POR pulse width of 100 ms allows serial flash devices with
65 ms to 100 ms internal POR delay to be powered-up and ready to
receive the nSTATUS signal from Stratix III. When the PORSEL is set to
high, the POR signal pulse width is set to 12 ms. A POR pulse width of
12 ms allows time for power supplies to ramp-up to full rail.
1
V
V
V
V
V
Voltage Supply
V
V
V
V
V
Power Supply
Table 10–1. Power Supplies Monitored by the POR Circuitry
Table 10–2. Power Supplies That Are Not Monitored by the POR Circuitry
CC
CCL
CCPT
CCPD
CCPGM
CCIO
CCA_PLL
CCD_PLL
CC_CLKIN
CCBAT
Refer to the
the Stratix III Device Handbook for more information on the POR
specification.
I/O power supply
PLL analog global power supply
PLL digital power supply
PLL differential clock input power supply
(top and bottom I/O banks only)
Battery back-up power supply for design
security volatile key storage
I/O registers power supply
Selectable core voltage power supply
Power supply for the programmable
power technology
I/O pre-driver power supply
Configuration pins power supply
DC and Switching Characteristics
Description
Description
chapter, volume 2 of
1.1
0.9, 1.1
2.5
2.5, 3.0, 3.3
1.8, 2.5, 3.0, 3.3
1.2, 1.5, 1.8, 2.5,
3.0, 3.3
2.5
1.1
2.5
2.5
Table
Altera Corporation
Setting (V)
Setting (V)
October 2007
10–1:
Table
10–2: