EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 202

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–52
Stratix III Device Handbook, Volume 1
PLL Reconfiguration
Phase-locked loops (PLLs) use several divide counters and different
voltage-controlled oscillator (VCO) phase taps to perform frequency
synthesis and phase shifts. In Stratix III PLLs, you can reconfigure both
the counter settings and phase-shift the PLL output clock in real time.
You can also change the charge pump and loop-filter components, which
dynamically affects the PLL bandwidth. You can use these PLL
components to update the output-clock frequency and the PLL
bandwidth and to phase-shift in real time, without reconfiguring the
entire Stratix III device.
The ability to reconfigure the PLL in real time is useful in applications
that operate at multiple frequencies. It is also useful in prototyping
environments, allowing you to sweep PLL output frequencies and adjust
the output-clock phase dynamically. For instance, a system generating
test patterns is required to generate and transmit patterns at 75 or
150 MHz, depending on the requirements of the device under test.
Reconfiguring the PLL components in real time allows you to switch
between two such output frequencies within a few microseconds. You
can also use this feature to adjust clock-to-out (t
changing the PLL output clock phase shift. This approach eliminates the
need to regenerate a configuration file with the new PLL settings.
PLL Reconfiguration Hardware Implementation
The following PLL components are reconfigurable in real time:
■
■
■
■
■
Figure 6–37
by shifting their new settings into a serial shift-register chain or scan
chain. Serial data is input to the scan chain via the scandataport and
shift registers are clocked by scanclk. The maximum scanclk
frequency is 100 MHz. Serial data is shifted through the scan chain as
long as the scanclkena signal stays asserted. After the last bit of data is
clocked, asserting the configupdate signal for at least one scanclk
clock cycle causes the PLL configuration bits to be synchronously
updated with the data in the scan registers.
Pre-scale counter (n)
Feedback counter (m)
Post-scale output counters (C0 - C9)
Post VCO Divider (K)
Dynamically adjust the charge-pump current (Icp) and loop-filter
components (R, C) to facilitate reconfiguration of the PLL bandwidth
shows how PLL counter settings can be dynamically adjusted
CO
) delays in real time by
Altera Corporation
November 2007