EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 535

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
(4)
DDR2 SDRAM
DDR SDRAM
Table 1–27. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate
Controller
Memory Standards
Numbers are based on full-rate controller and are preliminary until characterization is final.
DDR3 SDRAM, QDRII/QDRII+ SRAM, and RLDRAM II support will be evaluated for a future version of the
Quartus II software.
Performance is based on 0.9-V core voltage. At 1.1-V core voltage, the -4L speed grade devices have the same
performance as the -4 speed grade devices.
This applies for interfaces with both modules and components.
Table
Note
(4)
1–27:
(4)
(1),
(2)
I/O Banks
Bottom
–2 Speed Grade
Top/
267
200
External Memory I/O Timing Specifications
Table 1–28
read and write data paths. Use these specifications to determine timing
margins for source synchronous paths between the Stratix III FPGA and
the external memory device. Refer to the figure for “SW (sampling
window)” in
Speed Grade
(MHz)
Commercial
Table 1–28. Sampling Window (SW) - Read Side (Part 1 of 2) - Preliminary
-2
-3
-4
-2
-3
-4
-4
-2
Banks
Right
Left/
267
200
I/O
and
Stratix III Device Datasheet: DC and Switching Characteristics
Table
Table 1–29
I/O Banks
Bottom
–3 Speed Grade
Top/
233
200
Location
1–206.
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
(MHz)
list Stratix III device timing uncertainties on the
Banks
Right
Left/
233
200
I/O
Memory Type
QDRII / II +
Bottom
Stratix III Device Handbook, Volume 2
Banks
–4 Speed Grade
DDR2
DDR2
DDR2
DDR3
DDR3
DDR3
DDR1
Top/
200
200
I/O
(MHz)
Banks
Right
Left/
200
200
I/O
Sampling Window (ps)
Setup
250
300
374
250
300
374
250
260
-4L Speed Grade
Bottom
Banks
Top/
167
167
I/O
(MHz)
(3)
Banks
Right
Left/
Hold
167
167
I/O
250
300
374
250
300
374
250
260
1–23