EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 7

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Contents
Chapter 8. External Memory Interfaces in Stratix III Devices
Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Altera Corporation
Design Considerations ........................................................................................................................ 7–46
Conclusion ............................................................................................................................................ 7–50
Referenced Documents ....................................................................................................................... 7–50
Introduction ............................................................................................................................................ 8–1
Memory Interfaces Pin Support .......................................................................................................... 8–6
Stratix III External Memory Interface Features ............................................................................... 8–21
Conclusion ............................................................................................................................................ 8–45
Referenced Documents ....................................................................................................................... 8–46
Document Revision History ............................................................................................................... 8–46
Introduction ............................................................................................................................................ 9–1
I/O Banks ................................................................................................................................................ 9–2
LVDS Channels ...................................................................................................................................... 9–3
Differential Transmitter ........................................................................................................................ 9–4
Programmable Pre-Emphasis and Programmable VOD ............................................................... 9–12
Differential I/O Termination ............................................................................................................. 9–13
Left/Right PLLs (PLL_Lx/ PLL_Rx) ................................................................................................ 9–14
Clocking ................................................................................................................................................ 9–15
Differential Pin Placement Guidelines ............................................................................................. 9–21
Differential I/O Standards Termination ..................................................................................... 7–39
I/O Termination ............................................................................................................................. 7–46
I/O Banks Restrictions .................................................................................................................. 7–47
I/O Placement Guidelines ............................................................................................................ 7–48
Data and Data Clock/Strobe Pins .................................................................................................. 8–6
Optional Parity, DM, BWSn, ECC and QVLD Pins ................................................................... 8–18
Address and Control/Command Pins ........................................................................................ 8–19
Memory Clock Pins ........................................................................................................................ 8–20
DQS Phase-Shift Circuitry ............................................................................................................ 8–21
DQS Logic Block ............................................................................................................................. 8–32
Leveling Circuitry .......................................................................................................................... 8–36
Dynamic On-Chip Termination Control ..................................................................................... 8–38
I/O Element (IOE) Registers ........................................................................................................ 8–39
IOE Features .................................................................................................................................... 8–43
PLL ................................................................................................................................................... 8–45
Receiver Data Realignment Circuit (Bit Slip) ............................................................................... 9–9
Dynamic Phase Aligner (DPA) ..................................................................................................... 9–10
Soft-CDR Mode ............................................................................................................................... 9–11
Synchronizer ................................................................................................................................... 9–12
Source-Synchronous Timing Budget ........................................................................................... 9–16
Differential Data Orientation ........................................................................................................ 9–17
Differential I/O Bit Position ......................................................................................................... 9–17
Receiver Skew Margin for Non-DPA .......................................................................................... 9–19
Guidelines for DPA-Enabled Differential Channels ................................................................. 9–21
Guidelines for DPA-Disabled Differential Channels ................................................................ 9–29
Contents
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