EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 392

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Passive Serial Configuration
11–32
Stratix III Device Handbook, Volume 1
Figure 11–13. Single Device PS Configuration Using an External Host
Note to
(1)
Upon power-up, Stratix III devices go through a POR. The POR delay is
dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. When PORSEL is driven high, the
POR time is approximately 12 ms. During POR, the device resets, holds
nSTATUS low, and tri-states all user I/O pins. Once the device
successfully exits POR, all user I/O pins continue to be tri-stated. If
nIO_pullup is driven low during power-up and configuration, the user
I/O pins and dual-purpose I/O pins will have weak pull-up resistors
which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the MAX II device must generate a low-to-high
transition on the nCONFIG pin.
1
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device should place the configuration data one
bit at a time on the DATA0 pin. If you are using configuration data in .rbf,
Connect the pull-up resistor to a supply that provides an acceptable input signal
for the device. V
on the device and the external host.
(MAX II Device or
Microprocessor)
External Host
ADDR
Figure
V
configuration and JTAG pins reside, need to be fully powered to
the appropriate voltage levels in order to begin the
configuration process.
Memory
CC
, V
11–13:
DATA0
CCIO
CC
, V
should be high enough to meet the V
CCPGM
10 k Ω
(1)
and V
VCC
10 k Ω
CCPD
VCC
GND
(1)
, of the banks where the
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device
IH
specification of the I/O
MSEL2
MSEL1
MSEL0
Altera Corporation
nCEO
November 2007
N.C.
GND
V
CCPGM