EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 174

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–16. Stratix III PLL Locations
6–24
Stratix III Device Handbook, Volume 1
Left/Right PLLs
Left/Right PLLs
PLL_L1_CLK
PLL_L4_CLK
CLK[0..3]
L1
L2
L3
L4
Figure 6–16
Stratix III PLL Hardware Overview
Stratix III devices contain up to 12 PLLs with advanced clock
management features. The main goal of a PLL is to synchronize the phase
and frequency of an internal or external clock to an input reference clock.
There are a number of components that comprise a PLL to achieve this
phase alignment.
Stratix III PLLs align the rising edge of the input reference clock to a
feedback clock using the phase-frequency detector (PFD). The falling
edges are determined by the duty-cycle specifications. The PFD produces
an up or down signal that determines whether the voltage-controlled
oscillator (VCO) needs to operate at a higher or lower frequency. The
output of the PFD feeds the charge pump and loop filter, which produces
a control voltage for setting the VCO frequency. If the PFD produces an
up signal, then the VCO frequency increases. A down signal decreases
the VCO frequency. The PFD outputs these up and down signals to a
Top/Bottom PLLs
Top/Bottom PLLs
shows the location of PLLs in Stratix III devices.
CLK[12..15]
CLK[4..7]
Q1
Q4
B1 B2
T1
T2
Q2
Q3
Top/Bottom PLLs
Top/Bottom PLLs
R1
R2
R3
R4
PLL_R1_CLK
CLK[8..11]
PLL-R4_CLK
Altera Corporation
November 2007
Left/Right PLLs
Left/Right PLLs