EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 399

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
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PS Configuration Using a Microprocessor
In this PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Stratix III device.
Refer to the
Host”
is also applicable when using a microprocessor as an external host.
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB-Blaster™ universal serial bus (USB) port download cable,
MasterBlaster™ serial/USB communications cable, ByteBlaster II parallel
port download cable, ByteBlasterMV™ parallel port download cable, and
the EthernetBlaster™ download cable.
In PS configuration with a download cable, an intelligent host (such as a
PC) transfers data from a storage device to the device via the USB Blaster,
MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable.
Upon power-up, the Stratix III devices go through a POR. The POR delay
is dependent on the PORSEL pin setting. When PORSEL is driven low, the
POR time is approximately 100 ms. If PORSEL is driven high, the POR
time is approximately 12 ms. During POR, the device will reset, hold
nSTATUS low, and tri-state all user I/O pins. Once the device successfully
exits POR, all user I/O pins continue to be tri-stated. If nIO_pullup is
driven low during power-up and configuration, the user I/O pins and
dual-purpose I/O pins will have weak pull-up resistors which are on
(after POR) before and during configuration. If nIO_pullup is driven
high, the weak pull-up resistors are disabled.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-kΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
section for all configuration and timing information. This section
To begin configuration, power the V
V
pins reside) to the appropriate voltage levels.
CCPD
“PS Configuration Using a MAX II Device as an External
voltages (for the banks where the configuration and JTAG
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
CC
, V
CCIO
, V
CCPGM
, and
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