EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 91

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 4–13. Stratix III True Dual-Port Timing Waveform
Altera Corporation
November 2007
q_a (asynch)
q_b (asynch)
address_a
address_b
data_a
wren_a
wren_b
clk_a
clk_b
din-1
doutn-1
an-1
bn
din-1
din
an
Figure 4–13
operation at port A and read operation at port B with the
Read-During-Write behavior set to new data. Registering the RAM's
outputs would simply delay the q outputs by one clock cycle.
Shift-Register Mode
All Stratix III memory blocks support shift register mode. Embedded
memory block configurations can implement shift registers for digital
signal processing (DSP) applications, such as finite impulse response
(FIR) filters, pseudo-random number generators, multi-channel filtering,
and auto- and cross-correlation functions. These and other DSP
applications require local data storage, traditionally implemented with
standard flip-flops that quickly exhaust many logic cells for large shift
registers. A more efficient alternative is to use embedded memory as a
shift-register block, which saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data
width (w), the length of the taps (m), and the number of taps (
cascade memory blocks to implement larger shift registers.
doutn
din
b0
a0
shows true dual-port timing waveforms for the write
dout0
a1
TriMatrix Embedded Memory Blocks in Stratix III Devices
dout0
dout1
b1
a2
dout2
Stratix III Device Handbook, Volume 1
a3
dout3
dout1
b2
din4
a4
din4
din5
a5
n
dout2
). You can
din5
b3
din6
a6
4–17