EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 404

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

JTAG Configuration
11–44
Stratix III Device Handbook, Volume 1
TDI
TDO
TMS
TCK
TRST
Pin Name
Table 11–11. Dedicated JTAG Pins
Test data input
Test data output
Test mode select Input pin that provides the control signal to determine the transitions of the TAP
Test clock input
Test reset input
(optional)
Pin Type
f
The TDO output is powered by the V
For recommendations on how to connect a JTAG chain with multiple
voltages across the devices in the chain, refer to the
Boundary Scan Testing in Stratix III Devices
Handbook.
During JTAG configuration, you can download data to the device on the
PCB through the USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV download cable. Configuring devices through a cable is
similar to programming devices in-system, except you should connect the
TRST pin to V
Figure 11–19
Serial input pin for instructions as well as test and programming data. Data is
The clock input to the BST circuitry. Some operations occur at the rising edge
shifted in the rising edge of
board, you can disable the JTAG circuitry by connecting this pin to V
Serial data output pin for instructions as well as test and programming data. Data
is shifted out on the falling edge of
shifted out of the device. If the JTAG interface is not required on the board, you
can disable the JTAG circuitry by leaving this pin unconnected.
controller state machine. Transitions within the state machine occur on the rising
edge of
is evaluated on the rising edge of
the board, you can disable the JTAG circuitry by connecting this pin to V
while others occur at the falling edge. If the JTAG interface is not required on the
board, you can disable the JTAG circuitry by connecting this pin to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The
pin is optional according to IEEE Std. 1149.1. If the JTAG interface is not required
on the board, you can disable the JTAG circuitry by connecting this pin to GND.
TCK
. Therefore, you must set up
shows JTAG configuration of a single Stratix III device.
CC
. This ensures that the TAP controller is not reset.
TCK
. If the JTAG interface is not required on the
TCK
Description
TCK
. If the JTAG interface is not required on
. The pin is tri-stated if data is not being
CCPD
TMS
before the rising edge of
power supply of I/O bank 1A.
chapter of the Stratix III Device
IEEE 1149.1 (JTAG)
Altera Corporation
November 2007
CC
TCK
.
CC
TRST
.
.
TMS