EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 325

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 9–7. Data Realignment Timing
Altera Corporation
November 2007
rx_channel_data_align
rx_outclock
rx_out
rx_in
inclk
Receiver Data Realignment Circuit (Bit Slip)
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If the DPA
is enabled, the received data is captured with different clock phases on
each channel. This may cause the received data to be misaligned from
channel to channel. To compensate for this channel-to-channel skew and
establish the correct received word boundary at each channel, each
receiver channel has a dedicated data realignment circuit that realigns the
data by inserting bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of
each receiver independently controlled from the internal logic. The data
slips one bit for every pulse on the RX_CHANNEL_DATA_ALIGN. The
following are requirements for the RX_CHANNEL_DATA_ALIGN signal:
■
■
■
■
Figure 9–7
the deserialization factor set to 4.
The data realignment circuit can have up to 11 bit-times of insertion
before a rollover occurs. The programmable bit rollover point can be from
1 to 11 bit-times, independent of the deserialization factor. An optional
status port, RX_CDA_MAX, is available to the FPGA from each channel to
indicate when the preset rollover point is reached.
The minimum pulse width is one period of the parallel clock in the
logic array
The minimum low time between pulses is one period of parallel
clock
There is no maximum high or low time
Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN
3
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
shows receiver output (RX_OUT) after one bit slip pulse with
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Stratix III Device Handbook, Volume 1
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