EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 188

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–38
Stratix III Device Handbook, Volume 1
Figure 6–27
between PLL clocks in EFB mode.
Figure 6–27. Phase Relationship Between PLL Clocks in External-Feedback
Mode
Note to
(1)
Clock Multiplication and Division
Each Stratix III PLL provides clock synthesis for PLL output ports using
m/(n* post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match f
unique post-scale counter that divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets its frequency
specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range).
Then the post-scale counters scale down the VCO frequency for each
output port.
fbin Clock Input Pin
The PLL clock outputs can lead or lag the fbin clock input.
Clock Outputs (1)
Dedicated PLL
Figure
Clock Port (1)
PLL Clock at
the Register
PLL Reference
Clock at the
Input Pin
shows an example waveform of the phase relationship
6–27:
Phase Aligned
in
(m/n). Each output port has a
Altera Corporation
November 2007