EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 306

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–16. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Figure 8–17. DDR3 SDRAM Unbuffered Module Clock Topology
8–36
Stratix III Device Handbook, Volume 1
Postamble Enable
dqsenable
DQS
DQS/DQ
DQS/DQ
Leveling Circuitry
DDR3 SDRAM unbuffered modules use a fly-by clock distribution
topology for better signal integrity. This means that the CK/CK# signals
arrive at each DDR3 SDRAM device in the module at different times. The
difference in arrival time between the first DDR3 SDRAM device and the
last device on the module can be as long as 1.6 ns.
clock topology in DDR3 SDRAM unbuffered modules.
DQS/DQ
DQS/DQ
CK/CK#
DQS/DQ
DQS/DQ
Postamble
DQS/DQ
Postamble glitch
Figure 8–17
DQS/DQ
Preamble
Stratix III
Altera Corporation
Delayed by
1/2T logic
November 2007
shows the