NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 133

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.11.2.2
Intel
®
82801DB ICH4 Datasheet
Power Management
Attempting clock control with more than one processor is not feasible, because the Host controller
does not provide any indication as to which processor is executing a particular Stop-Grant cycle.
Without this information, there is no way for the ICH4 to know when it is safe to deassert
STPCLK#.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be connected
to both processors. However, for ACPI implementations, the ICH4 does not support the C2 state
for both processors, since there are not two processor control blocks. The BIOS must indicate that
the ICH4 only supports the C1 state for dual-processor designs. However, the THRM# signal can
be used for overheat conditions to activate thermal throttling.
When entering S1, the ICH4 asserts STPCLK# to both processors. To meet the processor
specifications, the CPUSLP# signal will have to be delayed until the second Stop-Grant cycle
occurs. To ensure this, the ICH4 waits a minimum or 60 PCI clocks after receipt of the first Stop-
Grant cycle before asserting CPUSLP# (if the SLP_EN bit is set to 1).
Both processors must immediately respond to the STPCLK# assertion with stop grant
acknowledge cycles before the ICH4 asserts CPUSLP# in order to meet the processor setup time
for CPUSLP#. Meeting the processor setup time for CPUSLP# is not an issue if both processors are
idle when the system is entering S1. If you cannot guarantee that both processors will be idle, do
not enable the SLP_EN bit. Note that setting SLP_EN to 1 is not required to support S1 in a dual-
processor configuration.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1 state, and thus
STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both processors will lose
power. Upon exit from those states, the processors will have their power restored.
Functional Description
133