NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 256

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LAN Controller Registers (B1:D8:F0)
7.1.9
7.1.10
7.1.11
256
Note: The ICH4’s integrated LAN controller requires one BAR for memory mapping. Software
PMLT—PCI Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
CSR_MEM_BASE CSR — Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
determines which BAR (memory or I/O) is used to access the Lan controller’s CSR registers.
31:12
11:4
Bit
7:3
2:0
Bit
6:0
Bit
2:1
7
3
0
Master Latency Timer Count (MLTC) — R/W. Defines the number of PCI clock cycles that the
integrated LAN controller may own the bus while acting as bus master.
Reserved
Multi-Function Device — RO. Hardwired to 0 to indicate a single function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration space as an
Ethernet controller.
Base Address — R/W. Upper 20 bits of the base address provides 4 KB of memory-Mapped space
for the LAN controller’s Control/Status Registers.
Reserved
Prefetchable — RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-Mapped
address range.
Type — RO. Hardwired to 00b to indicate the memory-Mapped address range may be located
anywhere in 32-bit address space.
Memory Space Indicator — RO. Hardwired to 0 to indicate that this base address maps to memory
space.
0Dh
00h
0Eh
00h
10
0000 0008h
–
13h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
R/W
8 bits
RO
8 bits
R/W, RO
32 bits
®
82801DB ICH4 Datasheet