NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 21

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Intel
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82801DB ICH4 Datasheet
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Short Message.............................................................................................117
APIC Bus Status Cycle Definition ................................................................118
Lowest Priority Message (Without Focus Processor) ..................................119
Remote Read Message ...............................................................................120
Interrupt Message Address Format .............................................................123
Interrupt Message Data Format ...................................................................124
Stop Frame Explanation ..............................................................................125
Data Frame Format......................................................................................126
Configuration Bits Reset By RTCRST# Assertion .......................................129
INIT# Going Active.......................................................................................131
NMI Sources ................................................................................................132
DP Signal Differences..................................................................................132
Frequency Strap Behavior Based on Exit State...........................................134
Frequency Strap Bit Mapping ......................................................................134
General Power States for Systems Using Intel
State Transition Rules for Intel
System Power Plane....................................................................................137
Causes of SMI# and SCI .............................................................................138
Break Events................................................................................................139
Sleep Types .................................................................................................142
Causes of Wake Events...............................................................................143
GPI Wake Events.........................................................................................143
Transitions Due to Power Failure.................................................................144
Transitions Due to Power Button .................................................................146
Transitions Due to RI# Signal ......................................................................147
Write Only Registers with Read Paths in ALT Access Mode.......................149
PIC Reserved Bits Return Values................................................................150
Register Write Accesses in ALT Access Mode............................................151
Intel
Alert on LAN* Message Data .......................................................................158
GPIO Implementation ..................................................................................159
IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) .....163
Interrupt/Active Bit Interaction Definition......................................................168
UltraATA/33 Control Signal Redefinitions ....................................................169
Frame List Pointer Bit Description ...............................................................172
TD Link Pointer ............................................................................................173
TD Control and Status .................................................................................174
TD Token .....................................................................................................176
TD Buffer Pointer .........................................................................................176
Queue Head Block.......................................................................................177
Queue Head Link Pointer.............................................................................177
Queue Element Link Pointer ........................................................................177
Command Register, Status Register, and TD Status Bit Interaction ...........180
Queue Advance Criteria...............................................................................182
USB Schedule List Traversal Decision Table ..............................................183
PID Format...................................................................................................185
PID Types ....................................................................................................185
Address Field ...............................................................................................186
Endpoint Field ..............................................................................................186
Token Format...............................................................................................187
IDE Transaction Timings (PCI Clocks) .......................................................164
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ICH4 Clock Inputs ..............................................................................152
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ICH4 .........................................................136
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ICH4 ................................135
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