NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 203

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.17.8.2
Intel
®
82801DB ICH4 Datasheet
the USB UHCI controller owns the port. Owning the port means that the differential output is
driven by the owner and the input stream is only visible to the owner. The host controller that is not
the owner of the port internally sees a disconnected port.
Note that the port-routing logic is the only block of logic within the ICH4 that observes the
physical (real) connect/disconnect information. The port status logic inside each of the host
controllers observes the electrical connect/disconnect information that is generated by the port-
routing logic.
Only the differential signal pairs are muxed/demuxed between the USB UHCI and USB EHCI host
controllers. The other USB functional signals are handled as follows:
The Port-Routing logic is implemented in the Suspend power well so that re-enumeration and re-
mapping of the USB ports is not required following entering and exiting a system sleep state in
which the core power is turned off.
The ICH4 also allows the USB Debug Port traffic to be routed in and out of Port #0. When in this
mode, the EHC is the owner of Port #0.
Device Connects
Section 4.2 of the Enhanced Host Controller Interface (EHCI) for Universal Serial Bus
Specification describes the details of handling Device Connects. There are four general scenarios
that are summarized below.
1. Configure Flag = 0 and a USB Full-speed/Low-speed -only Device is connected
2. Configure Flag = 0 and an USB High-speed-capable Device is connected
3. Configure Flag = 1 and a USB Full-speed/Low-speed-only Device is connected
4. Configure Flag = 1 and an USB High-speed-capable Device is connected
•
The Overcurrent inputs (OC#[5:0]) are directly routed to both controllers. An overcurrent
event is recorded in both controller’s status registers.
— In this case, the USB UHCI controller is the owner of the port both before and after the
— In this case, the USB UHCI controller is the owner of the port both before and after the
— In this case, the USB EHCI controller is the owner of the port before the connect occurs.
— In this case, the USB EHCI controller is the owner of the port before, and remains the
connect occurs. The EHC (except for the port-routing logic) never sees the connect occur.
The UHCI driver handles the connection and initialization process.
connect occurs. The EHC (except for the port-routing logic) never sees the connect occur.
The UHCI driver handles the connection and initialization process. Since the USB UHCI
controller does not perform the high-speed chirp handshake, the device operates in
compatible mode.
The EHCI driver handles the connection and performs the port reset. After the reset
process completes, the EHC hardware has cleared (not set) the Port Enable bit in the
EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner bit in the
same register, causing the USB UHCI controller to see a connect event and the EHC to see
an “electrical” disconnect event. The UHCI driver and hardware handle the connection
and initialization process from that point on. The EHCI driver and hardware handle the
perceived disconnect.
owner after, the connect occurs. The EHCI driver handles the connection and performs the
port reset. After the reset process completes, the EHC hardware has set the Port Enable bit
in the EHC’s PORTSC register. The port is functional at this point. The USB UHCI
controller continues to see an unconnected port.
Functional Description
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