NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 347

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

9.8.1.2
Intel
®
82801DB ICH4 Datasheet
GEN_PMCON_2—General PM Configuration 2 Register (PM—D31:F0)
Offset Address:
Default Value:
Lockable:
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
Bit
6:5
7
4
3
2
1
0
period may not be detected by the ICH4.
Reserved
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the processor
needs to lock its PLLs. This is used where timing t208 applies (see
00 = Minimum lock time of 30.7 µs (Default)
01 = min 61.4 µs,
10 = min 122.8 µs, and
11 = min 245.6 µs.
System Reset Status (SRS) — R/WC. Intel
pressed. BIOS is expected to read this bit and clear it if it is set. This bit is also reset by RSMRST#
and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC. This bit is set when PCIRST# is inactive and
CPUTHRMTRIP# goes active while the system is in an S0 or S1 state. This bit is also reset by
RSMRST# and CF9h resets. It is not reset by the shutdown and reboot associated with the
CPUTHRMTRIP# event.
Reserved
CPU Power Failure (CPUPWR_FLR) — R/WC.
0 = Software clears this bit by writing a 0 to the bit position.
1 = Indicates that the VRMPWRGD signalfrom the processor’s VRM went low.
PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position, or when the system goes into a G3
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. The bit
NOTES:
1. Traditional designs have a reset button logically AND’d with the PWROK signal from the power
2. In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD.
supply and the CPU’s voltage regulator module. If this is done with the ICH4, the PWROK_FLR
bit will be set. The ICH4 treats this internally as if the RSMRST# signal had gone active.
However, it is not treated as a full power failure. If PWROK goes inactive and then active (but
RSMRST# stays high), then the ICH4 will reboot (regardless of the state of the AFTERG3 bit). If
the RSMRST# signal also goes low before PWROK goes high, then this is a full power failure,
and the reboot policy is controlled by the AFTERG3 bit.
state.
will be cleared only by software by writing a 1 to this bit or when the system goes to a G3 state.
A2h
00h
No
®
Description
ICH4 sets this bit when the SYS_RESET# button is
Attribute:
Size:
Usage:
Power Well:
LPC Interface Bridge Registers (D31:F0)
Chapter
R/WC, R/W
8 bit
ACPI, Legacy
Resume
17).
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