NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 356

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.2
356
PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
15:11
7:6
4:1
Bit
10
9
8
5
0
Reserved
RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event to wake
after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button
Override event.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS goes active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes
Reserved.
Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting of the
PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no
effect on the PWRBTN_STS bit being set by the assertion of the power button. The Power Button is
always enabled as a Wake event.
0 = Disable.
1 = Enable.
Reserved.
Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS are set, an SCI is
raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
Reserved.
Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with the SCI_EN bit
as described below:
TMROF_EN
0
1
1
active.
PMBASE + 02h
(
0000h
No
Bits 0
Bits 8
Bit 10: RTC
ACPI PM1a_EVT_BLK + 2)
SCI_EN
–
–
x
0
1
7: Core,
9, 11
–
15: Resume
Effect when TMROF_STS is set
No SMI# or SCI
SMI#
SCI
Description
Attribute:
Size:
Usage:
Intel
R/W
16 bit
ACPI or Legacy
®
82801DB ICH4 Datasheet