NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 165

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.15.2.1
5.15.2.2
Intel
®
Figure 5-14. Physical Region Descriptor Table Entry
82801DB ICH4 Datasheet
Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region Descriptor (PRD).
The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until
all regions described by the PRDs in the table have been transferred. Note that the ICH4 bus master
IDE function does not support memory regions or Descriptor tables located on ISA.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8 bytes in
length. The first 4 bytes specify the byte address of a physical memory region. This memory region
must be DWord aligned and must not cross a 64-KB boundary. The next two bytes specify the size
or transfer count of the region in bytes (64-KB limit per region). A value of zero in these two bytes
indicates 64 KB (thus, the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it
indicates that this is the final PRD in the Descriptor table. Bus master operation terminates when
the last descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base
Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of
the Base Address is not masked and if set, causes the lower Word byte enables to be deasserted for
the first DWord transfer. The write to PCI typically consists of a 32-byte cache line. If valid data
ends prior to end of the cache line, the byte enables are deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater
than the size of the disk transfer request. If greater than the disk transfer request, the driver must
terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to
0) when the drive issues an interrupt to signal transfer completion.
Line Buffer
A single line buffer exists for the ICH4 Bus master IDE interface. This buffer is not shared with
any other function. The buffer is maintained in either the read state or the write state. Memory
writes are typically 4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer
allows burst data transfers to proceed at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the
controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in
last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These
events may occur prior to line buffer emptying for memory writes. If either of these conditions
exist, all PCI Master non-memory read accesses to ICH4 are retried until all data in the line buffers
has been transferred to memory.
EOT
Memory Region Physical Base Address [31:1]
Byte 3
Reserved
Byte 2
Byte Count [15:1]
Byte 1
Byte 0
0
0
Main Memory
Functional Description
Memory
Region
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