NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 148

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.12.8.5
5.12.9
148
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the ICH4
immediately transitions to an S5 state. However, since the processor has overheated, it does not
respond to the ICH4’s STPCLK# pin with a stop grant special cycle. Therefore, the ICH4 does not
wait for one. Immediately upon seeing THRMTRIP# low, the ICH4 initiates a transition to the S5
state, drives SLP_S3#, SLP_S4#, SLP_S5# low, and sets the CTS bit. The transition looks like a
power button override.
It is extremely important that when a THRMTRIP# event occurs, the ICH4 power down
immediately without following the normal S0 -> S5 path. This path may be taken in parallel, but
ICH4 must immediately enter a power down state. It will do this by driving SLP_S3#, SLP_S4#,
and SLP_S5# immediately after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very unlikely)
that components around it (e.g., the ICH4, are no longer executing cycles properly). Therefore, if
THRMTRIP# fires, and the ICH4 is relying on state machine logic to perform the power down, the
state machine may not be working, and the system will not power down.
The ICH4 follows this flow for THRMTRIP#.
ALT Access Mode
Before entering a low power state, several registers from powered down parts may need to be
saved. In the majority of cases, this is not an issue, as registers have read and write paths. However,
several of the ISA compatible registers are either read only or write only. To get data out of write-
only registers, and to restore data into read-only registers, the ICH4 implements an ALT access
mode.
If the ALT access mode is entered and exited after reading the registers of the ICH4 timer (8254),
the timer starts counting faster (13.5 ms). The following steps listed below can cause problems:
After getting control in step #3, if the OS does not reprogram the system timer again, the timer
ticks may be happening faster than expected. For example DOS and its associated software assume
that the system timer is running at 54.6 ms and as a result the timeouts in the software may be
happening faster than expected.
Operating systems (e.g., Microsoft Windows* 98, Windows* 2000 and Windows NT*) reprogram
the system timer and, therefore, will not run into this problem.
1. At boot (PCIRST# low), THRMTRIP# ignored.
2. After power-up (PCIRST# high), if THRMTRIP# sampled active, SLP_S3#, SLP_S4#, and
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay active, even if
4. If S5 state reached, go to step #1, otherwise stay here. If the ICH4 never reaches S5, ICH4 will
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SLP_S5# fire, and normal sequence of sleep machine starts.
THRMTRIP# is now inactive. This is the equivalent of “latching” the thermal trip event.
not reboot until power is cycled.
BIOS enters ALT access mode for reading the ICH4 timer related registers.
BIOS exits ALT access mode.
BIOS continues through the execution of other needed steps and passes control to the OS.
Intel
®
82801DB ICH4 Datasheet