NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 197

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.17.3.1
Intel
®
82801DB ICH4 Datasheet
Note: Prefetching is limited to the current and next microframes only.
Note: Once the PDE checks the length of a periodic packet against the remaining time in the microframe
Periodic List Execution
The Periodic DMA engine contains buffering for two control structures (two transactions). By
implementing two entries, the EHC is able to pipeline the memory accesses for the next transaction
while executing the current transaction on the USB ports. Note that a multiple-packet, High-
Bandwidth transaction occupies one of these buffer entries, which means that up to six, 1-KB data
packets may be associated with the two buffered control structures.
5.17.3.1.1 Read Policies for Periodic DMA
The Periodic DMA engine performs reads for the following structures.
The EHC Periodic DMA Engine (PDE) does not generate accesses to main memory unless all three
of the following conditions are met.
(late-start check) and decides that there is not enough time to run it on the wire, then the EHC
switches over to run asynchronous traffic.
Periodic Frame List entry
iTD
siTD
qTD
Queue Head
Out Data
Frame Span Transversal
Node
Memory Structure
— The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this bit
— The Periodic Schedule Status bit is 1 (memory space, offset 24h, bit 14). Software sets this
— The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
indirectly by setting the RUN/STOP bit to 1.
bit indirectly by setting the Periodic Schedule Enable Bit to 1.
Size (DWords)
Up to 257
23
13
17
1
9
2
The EHC reads the entry for each microframe. The frame list is
not internally cached across microframes.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The ICH4 breaks large read requests down into smaller aligned
read requests based on the setting of the Read Request Max
Length field.
Comments
Functional Description
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