NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 200

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.17.6
5.17.6.1
200
USB EHCI Interrupts and Error Conditions
Section 4 of the EHCI specification goes into detail on the EHC interrupts and the error conditions
that cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only ICH4-specific interrupt and error-reporting behavior is documented in
this section. The EHCI Interrupts Section must be read first, followed by this section of the
datasheet to fully comprehend the EHC interrupt and error-reporting functionality.
Aborts on USB EHCI-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following
actions are taken when this occurs:
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The Host System Error status bit is set
The DMA engines are halted after completing up to one more transaction on the USB interface
If enabled (by the Host System Error Enable), an interrupt is generated
If the status is Master Abort, the Received Master Abort bit in configuration space is set
If the status is Target Abort, the Received Target Abort bit in configuration space is set
If enabled (by the SERR Enable bit in the function’s configuration space), the Signaled System
Error bit in configuration bit is set.
— Based on the EHC’s buffer sizes and buffer management policies, the Data Buffer Error
— Master Abort and Target Abort responses from hub interface on EHC-initiated read
— The ICH4 may assert the interrupts which are based on the interrupt threshold as soon as
— Since the ICH4 supports the 1024-element Frame List size, the Frame List Rollover
— The ICH4 delivers interrupts using PIRQ#[H].
— The ICH4 does not modify the CERR count on an Interrupt IN when the “Do Complete-
— For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not
can never occur on the ICH4.
packets will be treated as Fatal Host Errors. The EHC halts when these conditions are
encountered.
the status for the last complete transaction in the interrupt interval has been posted in the
internal write buffers. The requirement in the EHCI Specification (that the status is
written to memory) is met internally, even though the write may not be seen on the hub
interface before the interrupt is asserted.
interrupt occurs every 1024 milliseconds.
Split” execution criteria are not met.
get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to
that control structure do not fail the late-start test, then the “Missed Microframe” bit will
get set and written back.
Intel
®
82801DB ICH4 Datasheet