NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 374

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.9.6
374
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
15:5
Bit
4
3
2
1
0
Bit
3
2
1
0
Reserved
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. This allow the software to go directly
into pre-determined sleep state. This avoids race conditions.
0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3–S5
1 = Intel
Reserved
BOOT_STS — R/WC.
0 = Cleared by ICH4 based on RSMRST# or by software writing a 1 to this bit. Note that software
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched the
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the ICH4 will reboot
using the ‘safe’ multiplier (1111). This allows the system to recover from a CPU frequency multiplier
that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set and the
frequency multiplier is 1111, then the BIOS knows that the processor has been programmed to an
illegal multiplier.
SECOND_TO_STS — R/WC.
0 = This bit is cleared by writing a 1 to the bit position or by a RSMRST#.
1 = The ICH4 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably due
NOTE: BIOS should always clear this bit before executing SMBus reads and writes.
Intruder Detect (INTRD_DET) — R/WC.
0 = This bit is only cleared by writing a 1 to the bit position, or by RTCRST# assertion.
1 = Set by ICH4 to indicate that an intrusion was detected. This bit is set even if the system is in G3
TIMEOUT — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by ICH4 to indicate that the SMI was caused by the TCO timer reaching 0.
TCO_INT_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.
SW_TCO_SMI — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register.
NMI2SMI_STS — RO.
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the ICH4 when an SMI# occurs because an event occurred that would otherwise have
states. Software clears the bit by writing a 1 to this bit position.
should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit.
first instruction.
to system lock). If this bit is set and the NO_REBOOT configuration bit is 0, then the ICH4 will
reboot the system after the second timeout. The reboot is done by asserting PCIRST#.
state.
caused an NMI (because NMI2SMI_EN is set).
®
ICH4 sets this bit to 1 when it receives the SMI message on the SMLink's Slave Interface.
TCOBASE +06h
0000h
No
Description
Description
Attribute:
Size:
Power Well:
Intel
R/WC
16 bit
Resume
(Except Bit 0, in RTC)
®
82801DB ICH4 Datasheet