NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 508

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

AC ’97 Modem Controller Registers (D31:F6)
15.2.9
508
GLOB_STA—Global Status Register
I/O Address:
Default Value:
Lockable:
On reads from a codec, the controller will give the codec a maximum of 4 frames to respond, after
which if no response is received, it will return a dummy read completion to the processor (with all
F’s on the data) and also set the Read Completion Status bit in the Global Status Register.
Reads across DWord boundaries are not supported.
31:30
23:22
21:20
19:18
Bit
29
28
27
26
25
24
17
16
Reserved.
AC_SDIN2 Resume Interrupt (S2RI)
AC_SDIN[2].
0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN2 Codec Ready (S2CR)
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Bit Clock Stopped (BCS)
0 = Running. It is cleared if a transition is found on BIT_CLK.
1 = Stopped. This bit is set if the ICH4 detects that there has been no transition on BIT_CLK for
S/PDIF Interrupt (SPINT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that the S/PDIF out channel interrupt status bits have been set.
PCM In 2 Interrupt (P2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the PCM In 2 channel status bits have been set.
Microphone 2 In Interrupt (M2INT)
0 = When the specific status bit is cleared, this bit will be cleared.
1 = Indicates that one of the Mic in channel interrupts status bits has been set.
Sample Capabilities
00 = Reserved
01 = 16 and 20-bit Audio supported (ICH4 value)
10 = Reserved
11 = Reserved
Multichannel Capabilities
Out.
Reserved.
MD3 — R/W. Power down semaphore for Modem. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the AD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and maintains
context across power states (except G3). The bit has no hardware function. It is used by software in
conjunction with the MD3 bit to coordinate the entry of the two codecs into D3 state.
This bit is not affected by D3
four consecutive PCI clocks.
MBAR + 40h
00300000h
No
—
RO. Indicates the capability to support more greater than 16-bit audio.
—
—
—
—
HOT
HOT
HOT
RO. Indicates that the bit clock is not running.
RO. Indicates the capability to support more 4 and 6 channels on PCM
RO.
RO.
to D0 Reset.
to D0 Reset.
to D0 Reset.
—
—
—
RO. Reflects the state of the codec ready bit in AC_SDIN[2].
RO.
R/WC. This bit indicates that a resume event occurred on
Description
Attribute:
Size:
Power Well:
Intel
RO, R/W, R/WC
32 bits
Core
®
82801DB ICH4 Datasheet