NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 236

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.19.2.16
5.19.2.17
5.19.2.18
5.19.2.19
5.19.2.20
5.19.2.21
5.19.2.22
236
Input Slot 3: PCM Record Left Channel
Input Slot 4: PCM Record Right Channel
Input Slot 6: Optional Dedicated Microphone Record Data
As shown in
rate slot request flags for all output slots of the controller. When a slot request bit is set by the
codec, the controller will return data in that slot in the next output frame. Slot request bits for slots
3 and 4 are always set or cleared in tandem (i.e., both are set or cleared).
When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read.
SLOTREQ bits are always valid independent of the slot 1 tag bit.
Input Slot 2: Status Data Port
The status data port receives 16-bit control register read data.
Input slot 3 is the left channel input of the codec. The ICH4 supports 16-bit sample resolution.
Samples transmitted to the ICH4 must be in left/right channel order.
Input slot 4 is the right channel input of the codec. The ICH4 supports 16-bit sample resolution.
Samples transmitted to the ICH4 must be in left/right channel order.
Input Slot 5: Modem Line
Input slot 5 contains MSB justified modem data. The ICH4 supports 16-bit sample resolution.
Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This
input channel supplements a true stereo output which enables more precise echo cancellation
algorithm for speakerphone applications. The ICH4 supports 16-bit resolution for slot 6 input.
Input Slots 7–11: Reserved
Input frame slots 7–11 are reserved for future use and should be stuffed with zeros by the codec,
per the AC ’97 specification.
Input Slot 12: I/O Status
The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data
returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the
codec I/O space. Only the 16 MSBs are used to return GPI status. In order for GPI events to cause
an interrupt, both the 'sticky' and 'interrupt' bits must be set for that particular GPIO pin in regs 50h
and 52h. Therefore, the interrupt will be signalled until it has been cleared by the controller, which
can be much longer than one frame.
Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data from the most
recent slot 12 is returned on reads from offset 54h/D4h.
•
•
Bit [19:4]: Control Register Read Data
Bit [3:0]: Reserved.
Table
5-101, slot 1 delivers codec control register read address and multiple sample
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82801DB ICH4 Datasheet