NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 430

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
12.1.28
430
SPECIAL_SMI—Intel Specific USB EHCI SMI Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
This register provides a mechanism for BIOS to provide USB EHCI related bug fixes and
workarounds. Writing a 1 to that bit location clears bits that are marked as Read/Write-Clear
(R/WC). Software should clear all SMI status bits prior to setting the global SMI enable bit and
individual SMI enable bit to prevent spurious SMI when returning from a powerdown.
31:28
27:22
15:12
11:6
Bit
21
20
19
18
17
16
5
4
Reserved — RO. Hardwired to 00h
SMI on PortOwner — R/WC.
0 = Software clears these bits by writing a 1 to the bit location.
1 = Bits 27:22 correspond to the Port Owner bits for ports 1 (22) through 6 (27). These bits are set
SMI on PMCSR — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR)
SMI on Async — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Async Schedule Enable bit transitioned from 1->0 or 0->1.
SMI on Periodic — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Periodic Schedule Enable bit transitioned from 1-to-0 or 0-to-1
SMI on CF — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = Configure Flag (CF) transitioned from 1-to-0 or 0-to-1.
SMI on HCHalted — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).
SMI on HCReset — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = HCRESET transitioned to 1.
Reserved — RO. Hardwired to 00h
SMI on PortOwner Enable — R/W.
0 = Disable
1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits are 1, the
SMI on PMSCR Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue an SMI.
SMI on Async Enable — R/W.
0 = Disable
1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue an SMI.
to 1 whenever the associated Port Owner bits transition from 0-to-1 or 1-to-0.
register.
host controller will issue an SMI. Unused ports should have their corresponding bits cleared.
Suspend
70
00000000h
–
73h
Description
Attribute:
Size:
Intel
R/WC, R/W
32 bits
®
82801DB ICH4 Datasheet