NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 166

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.15.2.3
5.15.2.4
5.15.2.5
166
Warning:
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The
DMA Timing Enable Only bits in the IDE Timing register can be used to program fast timing mode
for DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster
that its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI
clock that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted
on the next PCI clock and no more transfers take place until DMA request is asserted again.
Interrupts
Legacy Mode
The ICH4 is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.
This connection is done from the ISA pin, before any mask registers. This implies the following:
In this mode, the ICH4 does not drive the PCI Interrupt associated with this function. That is only
used in native mode.
Native Mode
In this case both the primary and secondary channels share an interrupt. It will be internally
connected to PIRQ[C]# (IRQ18 in APIC mode). The interrupt will be active-low and shared.
Behavioral notes in native mode are:
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following steps are
required:
1. Software prepares a PRD Table in system memory. The PRD Table must be DWord-aligned
2. Software provides the starting address of the PRD Table by loading the PRD Table Pointer
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the Command
•
•
•
•
•
Bus Master IDE devices are connected directly off of ICH4. IDE interrupts cannot be
communicated through PCI devices or the serial stream.
The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the interrupt
controllers. The IDE logic forces these signals inactive in such a way that the Serial IRQ
source may be used.
The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt controller can
come from other sources (Serial IRQ, PIRQx).
The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
When switching the IDE controller to native mode, the IDE Interrupt Pin register (see
Section
interrupt is still active when the masking ends, the interrupt will be allowed to be asserted.
and must not cross a 64-KB boundary.
Register. The direction of the data transfer is specified by setting the Read/Write Control bit.
The interrupt bit and Error bit in the Status register are cleared.
Register. The first entry in the PRD table is fetched and loaded into two registers which are not
10.1.19) will be masked. If an interrupt occurs while the masking is in place and the
Intel
®
82801DB ICH4 Datasheet