NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 304

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.23
9.1.24
304
GEN_STA—General Status Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
7:3
Bit
3:0
2
1
0
7
6
5
4
Reserved
SAFE_MODE — RO.
0 = Intel
1 = ICH4 sampled AC_SDOUT high on the rising edge of PWROK. ICH4 will force
NO_REBOOT — R/W-Special.
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout). This bit cannot be set to
1 = ICH4 will disable the TCO Timer system reboot feature. This bit is set either by hardware when
Reserved
Reserved. Read only as 0.
Reserved. Read only as 0.
Top-Block Swap Mode (TOP_SWAP) — R/W.
0 = Intel
1 = ICH4 inverts A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH
CPU BIST Enable (CPU_BIST_EN) — R/W.
0 = Disable.
1 = The INIT# signal will be driven active when CPURST# is active. INIT# will go inactive with the
NOTE: This bit is in the Resume well and is reset by RSMRST#, but not by PCIRST# nor CF9h
CPU Frequency Strap (FREQ_STRAP[3:0]) — R/W. These bits determine the internal frequency
multiplier of the processor. These bits can be reset to 1111 based on an external pin strap or via the
RTCRST# input signal. Software must program this field based on the processor’s specified
frequency. Note that this field is only writable when the SAFE_MODE bit is cleared to 0, and
SAFE_MODE is only cleared by PWROK rising edge. These bits are in the RTC well.
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
0 by software if the strap is set to No Reboot.
SPKR is sampled high on the rising edge of PWROK, or by software writing a 1 to the bit.
type of reset.
feature space).
same timings as the other CPU I/F signals (Hold Time after CPURST# inactive). Note that
CPURST# is generated by the memory controller hub, but the ICH4 has a hub interface special
cycle that allows the ICH4 to control the assertion/deassertion of CPURST#.
writes.
®
®
ICH4 sampled AC_SDOUT low on the rising edge of PWROK.
ICH4 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other
D4h
0Xh
No
D5h
0Fh
(upon RTCRST# assertion low)
2Fh
(if Safe Mode Strap is active)
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
RO, R/W-Special
8 bit
Core
R/W
8 bit
RTC
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82801DB ICH4 Datasheet