NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 302

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.22
302
GEN_CNTL — General Control Register (LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
31:26
23:22
19:18
17:14
10:9
Bit
25
24
21
20
13
12
11
Reserved
REQ[5]#/GNT[5]# PC/PCI Protocol Select (PCPCIB_SEL) — R/W.
0 = REQ[5]#/GNT[5]# pins function as a standard PCI REQ/GNT signal pair.
1 = PCI REQ[5]#/GNT[5]# signal pair use the PC/PCI protocol as REQ[B]#/GNT[B]. The
Hide ISA Bridge (HIDE_ISA) — R/W.
0 = The Intel
1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA
Reserved
CPU Break Event Indication Enable (FERR#-MUX-EN) — R/W.
0 = Disable. The ICH4 does not examine the FERR# signal during C2. (Default)
1 = Enables the ICH4 to examine the FERR# signal during a C2 state as a break event. (See
Reserved
SCRATCHPAD. These bits are provided for possible future use.
Reserved
Coprocessor Error Enable (COPR_ERR_EN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = When FERR# is low, ICH4 generates IRQ13 internally and holds it until an I/O write to port F0h.
Keyboard IRQ1 Latch Enable (IRQ1LEN) — R/W.
0 = IRQ1 bypasses the latch.
1 = The active edge of IRQ1 is latched and held until a port 60h read.
Mouse IRQ12 Latch Enable (IRQ12LEN) — R/W.
0 = IRQ12 bypasses the latch.
1 = The active edge of IRQ12 is latched and held until a port 60h read.
Reserved
corresponding bits in the GPIO_USE_SEL register must also be set to a 0. If the corresponding
bits in the GPIO_USE_SEL register are set to a 1, then the signals will be used as a GPI and
GPO.
to-ISA bridge.
bridge. This prevents the OS PCI PnP from getting confused by seeing two ISA bridges.
It is required for the ICH4 PCI address line AD22 to connect to the PCI-to-ISA bridge’s IDSEL
input. When this bit is set, the ICH4 will not assert AD22 during configuration cycles to the PCI-
to-ISA bridge.
Section 5.12.5
It will also drive IGNNE# active.
D0h–D3h
00000000h
No
®
ICH4 does not prevent AD22 from asserting during configuration cycles to the PCI-
for details.)
Description
Attribute:
Size:
Power Well:
Intel
R/W
32 bit
Core
®
82801DB ICH4 Datasheet