NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 289

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

8.1.29
8.1.30
Intel
®
82801DB ICH4 Datasheet
PCI_MAST_STS—PCI Master Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
ERR_CMD—Error Command Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
Lockable:
This register configures the ICH4’s Device 30 responses to various system errors. The actual
assertion of the internal SERR# (routed to cause NMI# or SMI#) is enabled via the PCI Command
register.
Bit
5:0
Bit
7:3
1:0
2
7
6
Reserved
SERR# Enable on Receiving Target Abort (SERR_RTA_EN) — R/W.
0 = Disable.
1 = Enable. When SERR_EN is set, the Intel
Reserved
Internal PCI Master Request Status (INT_MREQ_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The Intel
Internal LAN Master Request Status (LAN_MREQ_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The ICH4’s internal LAN controller has requested use of the PCI bus.
PCI Master Request Status (PCI_MREQ_STS) — R/WC. Allows software to see if a particular bus
master has requested use of the PCI bus. For example, bit 0 will be set if ICH4 has detected
REQ[0]# asserted and bit 5 will be set if ICH4 detected REQ[5]# asserted.
0 = Software clears these bits by writing a 1 to the bit position.
1 = The associated PCI master has requested use of the PCI bus.
82h
00h
90h
00h
No
®
ICH4’s internal DMA controller or LPC has requested use of the PCI bus.
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
®
Attribute:
Size:
Attribute:
Size:
Power Well:
ICH4 will report SERR# when SERR_RTA is set.
R/WC
8 bits
R/W
8 bit
Core
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