NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 164

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.15.1.4
5.15.1.5
5.15.1.6
5.15.2
164
Table 5-53. IDE Transaction Timings (PCI Clocks)
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP) on
a drive by drive basis via the IDETIM Register.
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary, 0170h secondary) results in
two back-to-back 16-bit transactions to the IDE data port. The 32-bit data port feature is enabled
for all timings, not just enhanced timing. For compatible timings, a shutdown and startup latency is
incurred between the two, 16-bit halves of the IDE transaction. This guarantees that the chip selects
will be deasserted for at least two PCI clocks between the two cycles.
PIO IDE Data Port Prefetching and Posting
The ICH4 can be programmed via the IDETIM registers to allow data to be posted to and
prefetched from the IDE data ports. Data prefetching is initiated when a data port read occurs. The
read prefetch eliminates latency to the IDE data ports and allows them to be performed back to
back for the highest possible PIO data transfer rates. The first data port read of a sector is called the
demand read. Subsequent data port reads from the sector are called prefetch reads. The demand
read and all prefetch reads must be the same size (16 or 32 bits).
Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI
bus after the data is received by the ICH4. The ICH4 will then run the IDE cycle to transfer the data
to the drive. If the ICH4 write buffer is non-empty and an unrelated (non-data or opposite channel)
IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is
transferred to the drive.
Bus Master Function
The ICH4 can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master
channels are provided, one channel for each IDE connector (primary and secondary). By
performing the IDE data transfer as a PCI Bus master, the ICH4 off-loads the processor and
improves system performance in multitasking environments. Both devices attached to a connector
can be programmed for bus master transfers, but only one device per connector can be active at a
time.
Non-Data Port Compatible
Data Port Compatible
Fast Timing Mode
IDE Transaction Type
Latency
Startup
4
3
2
IORDY Sample
Point (ISP)
2–5
11
6
Intel
Recovery Time
®
(RCT)
82801DB ICH4 Datasheet
1–4
22
14
Shutdown
Latency
2
2
2