NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 287

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

8.1.26
Intel
®
82801DB ICH4 Datasheet
DEVICE_HIDE—Secondary PCI Device Hiding Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Power Well:
This register allows software to “hide” PCI devices (0 through 5) in terms of configuration space.
Specifically, when PCI devices (0–5) are hidden, the configuration space is not accessible because
the PCI IDSEL pin does not assert. The ICH4 supports the hiding of 6 external devices (0 through
5), which matches the number of PCI request/grant pairs, and the ability to hide the integrated LAN
device by masking out the configuration space decode of LAN controller. Writing a 1 to this bit
will not restrict the configuration cycle to the PCI bus. This differs from bits 0 through 5 in which
the configuration cycle is restricted.
Hiding a PCI device can be useful for debugging, bug work-arounds, and system management
support. Devices should only be hidden during initialization before any configuration cycles are
run. This guarantees that the device is not in a semi-enable state.
15:9
Bit
7:6
8
5
4
3
2
1
0
Reserved
HIDE_DEV8 —R/W. Same as bit 0 of this register, except for device 8 (AD[24]), which is hardwired
to the integrated LAN device. This bit will not change the way the configuration cycle appears on
PCI bus
Reserved
HIDE_DEV5 —R/W. Same as bit 0 of this register, except for device 5 (AD[21]).
HIDE_DEV4 —R/W. Same as bit 0 of this register, except for device 4 (AD[20]).
HIDE_DEV3 —R/W. Same as bit 0 of this register, except for device 3 (AD[19]).
HIDE_DEV2 —R/W. Same as bit 0 of this register, except for device 2 (AD[18]).
HIDE_DEV1 —R/W. Same as bit 0 of this register, except for device 1 (AD[17]).
HIDE_DEV0 —R/W.
0 = PCI configuration cycles for this slot are not affected.
1 = Device 0 is hidden on the PCI bus. This is done by masking the IDSEL (keeping it low) for
configuration cycles to that device. Since the device will not see its IDSEL go active, it will not
respond to PCI configuration cycles and the processor will think the device is not present.
AD[16] is used as IDSEL for device 0.
44–45h
00h
00h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Attribute:
Size:
R/W
16 bits
287