NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 18

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

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17-10 Ultra ATA Mode (Sustained Burst) .............................................................. 542
17-11 Ultra ATA Mode (Pausing a DMA Burst) ..................................................... 543
17-12 Ultra ATA Mode (Terminating a DMA Burst) ............................................... 543
17-13 USB Rise and Fall Times............................................................................. 543
17-14 USB Jitter..................................................................................................... 544
17-15 USB EOP Width........................................................................................... 544
17-16 SMBus Transaction ..................................................................................... 544
17-17 SMBus Timeout ........................................................................................... 545
17-18 Power Sequencing and Reset Signal Timings............................................. 545
System Configuration ...................................................................................... 4
Intel
Example External RTC Circuit ....................................................................... 54
Example V5REF Sequencing Circuit ............................................................. 55
Conceptual System Clock Diagram ............................................................... 66
Primary Device Status Register Error Reporting Logic.................................. 69
Secondary Status Register Error Reporting Logic ......................................... 69
NMI# Generation Logic.................................................................................. 70
Integrated LAN Controller Block Diagram...................................................... 73
64-Word EEPROM Read Instruction Waveform............................................ 83
LPC Interface Diagram .................................................................................. 86
Typical Timing for LFRAME#......................................................................... 90
Abort Mechanism........................................................................................... 90
Intel
DMA Serial Channel Passing Protocol .......................................................... 96
DMA Request Assertion Through LDRQ# ..................................................... 99
Coprocessor Error Timing Diagram ............................................................. 131
Signal Strapping .......................................................................................... 134
Physical Region Descriptor Table Entry ...................................................... 165
Transfer Descriptor ...................................................................................... 173
Example Queue Conditions ......................................................................... 181
USB Data Encoding..................................................................................... 184
USB Legacy Keyboard Enable and Status Paths........................................ 193
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Intel
AC ’97 2.3 Controller-Codec Connection..................................................... 230
AC-Link Protocol.......................................................................................... 231
AC-Link Powerdown Timing ........................................................................ 238
SDIN Wake Signaling .................................................................................. 239
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Intel
Clock Timing ................................................................................................ 539
Valid Delay from Rising Clock Edge ............................................................ 539
Setup and Hold Times ................................................................................. 539
Float Delay................................................................................................... 540
Pulse Width.................................................................................................. 540
Output Enable Delay.................................................................................... 540
IDE PIO Mode.............................................................................................. 541
IDE Multiword DMA ..................................................................................... 541
Ultra ATA Mode (Drive Initiating a Burst Read) ........................................... 542
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ICH4 Interface Signals Block Diagram................................................. 38
ICH4 DMA Controller ........................................................................... 92
ICH4 USB Port Connections.............................................................. 202
ICH4 Based Audio Codec ’97 Specification, Revision 2.3 ................. 229
ICH4 Ballout (Topview—Left Side) .................................................... 512
ICH4 Ballout (Topview—Right Side).................................................. 513
Intel
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82801DB ICH4 Datasheet