FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 163

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.11.3
5.12.12
5.12.12.1
5.12.12.2
5.12.12.3
Intel
®
Table 5-47. Register Write Accesses in ALT Access Mode
82801DBM ICH4-M Datasheet
Note:
Read Only Registers with Write Paths in ALT Access Mode
The registers described in
restores these values after returning from a powered down state. These registers must be handled
special by software. When in normal mode, writing to the base address/count register also writes to
the current address/count register. Therefore, the base address/count must be written first, then the
part is put into ALT access mode and the current address/count register is written.
System Power Supplies, Planes, and Signals
Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes
active for the STR state (typically mapped to ACPI S3). Power must be maintained to the ICH4
resume well, and to any other circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to the
motherboard.
SLP_S1# Signal
The SLP_S1# signal will typically use this signal to cut power to non-critical subsystems while in
the S1-M state.
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid. PWROK
should go active no sooner than 10 ms after Vcc3_3 and Vcc1_5 have reached their nominal
values.
1. Traditional designs have a reset button logically ANDs with the PWROK signal from the
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that are less
3. In the case of true PWROK failure, PWROK will go low first before the VRMPWRGD/
I/O Address
power supply and the processor’s voltage regulator module. If this is done with the ICH4, the
PWROK_FLR bit will be set. The ICH4 treats this internally as if the RSMRST# signal had
gone active. However, it is not treated as a full power failure. If PWROK goes inactive and
then active (but RSMRST# stays high), then the ICH4 will reboot (regardless of the state of
the AFTERG3 bit). If the RSMRST# signal also goes low before PWROK goes high, then this
is a full power failure, and the reboot policy is controlled by the AFTERG3 bit.
than one RTC clock period may not be detected by the ICH4.
VGATE.
D0h
08h
Table 5-47
have write paths to them in ALT access mode. Software
DMA Status Register for channels 0–3.
DMA Status Register for channels 4–7.
Register Write Value
Functional Description
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