FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 186

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16
5.16.1
5.16.1.1
186
Table 5-56. Frame List Pointer Bit Description
USB UHCI Controllers (D29:F0, F1 and F2)
The ICH4 contains three USB UHCI Host Controllers. Each Host Controller includes a root hub
with two separate USB ports each, for a total of 6 USB ports. The ICH4 Host Controllers support
the standard Universal Host Controller Interface (UHCI) Specification, Revision 1.1.
Data Structures in Main Memory
This section describes the details of the data structures used to communicate control, status, and
data between software and the ICH4: Frame Lists, Transfer Descriptors, and Queue Heads. Frame
Lists are aligned on 4-kB boundaries. Transfer Descriptors and Queue Heads are aligned on
16-byte boundaries.
Frame List Pointer
The frame list pointer contains a link pointer to the first data object to be processed in the frame, as
well as the control bits defined in
•
•
•
31:4
3:2
Bit
1
0
Overcurrent detection on all 6 USB ports is supported. The overcurrent inputs are 5-V tolerant,
and can be used as GPIs if not needed.
The ICH4’s USB UHCI controllers are arbitrated differently than standard PCI devices to
improve arbitration latency.
The USB UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB High-speed signaling rates, instead of USB I/O buffers.
Frame List Pointer (FLP). This field contains the address of the first data object to be processed in
the frame and corresponds to memory address signals [31:4], respectively.
Reserved. These bits must be written as 0.
QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer
is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the ICH4 to perform the proper type
of processing on the item after it is fetched.
1 = QH
0 = TD
Terminate (T). This bit indicates to the ICH4 whether the schedule for this frame has valid entries in
it.
1 = Empty Frame (pointer is invalid).
0 = Pointer is valid (points to a QH or TD).
Table
5-56.
Description
Intel
®
82801DBM ICH4-M Datasheet