FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 504

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
14.2.1
504
Table 14-3. Native Audio Bus Master Control Registers (Sheet 2 of 2)
Note: Internal reset as a result of D3
registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well registers will not be
reset by the D3
Core Well registers and bits NOT reset by the D3
Resume Well registers and bits will NOT be reset by the D3
x_BDBAR—Buffer Descriptor Base Address Register
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single 32 bit read from address offset
00h. Reads across DWord boundaries are not supported.
66–67h
68–69h
•
•
•
•
Offset
60–63
31:3
5Ah
5Bh
6Ah
6Bh
64h
65h
80h
Bit
2:0
offset 2Ch
offset 30h
offset 34h – Codec Access Semaphore Register (CAS)
offset 30h
Buffer Descriptor Base Address [31:3] — R/W. These bits represent address bits 31:3. The data
should be aligned on 8 byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
Hardwired to 0.
Mnemonic
SP_PICB
SP_BAR
PI2_PIV
SP_CIV
PI2_CR
SP_PIV
SP_LVI
SP_SR
SP_CR
–
–
SDM
–
HOT
33h – bits[29,15,11:10,0] Global Status (GLOB_STA)
33h – bits[17:16] Global Status (GLOB_STA)
2Fh – bits[6:0] Global Control (GLOB_CNT)
NABMBAR + 00h (PIBDBAR), Attribute:
00000000h
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
No
to D0 transition.
PCM In 2 Prefetched Index Value
PCM In 2 Control Register
S/PDIF Buffer Descriptor List Base Address
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status Register
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control Register
SData_IN Map
HOT
to D0 transition will reset all the core well registers except the
Name
Description
HOT
Size:
Power Well:
to D0 transition:
HOT
Intel
to D0 transition:
®
82801DBM ICH4-M Datasheet
R/W
32 bits
Core
00000000h
Default
0001h
0000h
00h
00h
00h
00h
00h
00h
00h
R/W, RO
Access
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO