FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 269

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

7.1.5
7.1.6
7.1.7
7.1.8
Intel
®
82801DBM ICH4-M Datasheet
REVID—Revision ID Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
NOTE: Refer to the ICH4 Specification Update for the value of the Revision ID Register.
SCC—Sub-Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
BCC—Base-Class Code Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
CLS—Cache Line Size Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
7:0
7:0
7:0
7:5
4:3
2:0
Bit
Bit
Bit
Bit
Revision Identification Value — RO. This 8-bit value indicates the revision number for the
integrated LAN* Controller. The three least significant bits in this register may be overridden by the ID
and REV ID fields in the EEPROM.
Sub Class Code — RO . 8-bit value that specifies the sub-class of the device as an Ethernet
controller.
Base Class Code — RO . 8-bit value that specifies the base class of the device as a network
controller.
Reserved
Cache Line Size (CLS) — R/W.
00 = Memory Write and Invalidate (MWI) command will not be used by the integrated LAN* Controller.
01 = MWI command will be used with Cache Line Size set to 8 DWORDs (only set if a value of 08h is
10 = MWI command will be used with Cache Line Size set to 16 DWORDs (only set if a value of 10h
11 = Invalid. MWI command will not be used.
Reserved
written to this register).
is written to this register).
08h
See Note
0Ah
00h
0Bh
02h
0Ch
00h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
RO
8 bits
RO
8 bits
RO
8 bits
R/W
8 bits
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