FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 327

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.1.35
Intel
®
82801DBM ICH4-M Datasheet
FWH_DEC_EN2—FWH Decode Enable 2 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
This register determines which memory ranges will be decoded on the PCI bus and forwarded to
the FWH. The ICH4 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
7:4
Bit
3
2
1
0
Reserved
FWH_70_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FWH_60_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FWH_50_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FWH_40_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
1 = Enable the following ranges for the FWH
FF70 0000h
FF30 0000h
FF60 0000h
FF20 0000h
FF50 0000h
FF10 0000h
FF40 0000h
FF00 0000h
F0h
0Fh
–
–
–
–
–
–
–
–
FF7F FFFFh
FF3F FFFFh
FF6F FFFFh
FF2F FFFFh
FF5F FFFFh
FF1F FFFFh
FF4F FFFFh
FF0F FFFFh
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bits
327