FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 371

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
7:6
Bit
3:1
8
5
4
0
Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard resets caused
by a CF9 write.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any
Reserved
Global Status (GBL _STS) — R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS
Bus Master Status (BM_STS) — R/WC.
This bit will not cause a wake event, SCI or SMI#
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by the ICH4 when a bus master requests a break from the C3 state. Bus master activity
Reserved
Timer Overflow Status (TMROF_STS) — R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).
PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state
with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
other enable bit.
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if
SCI_EN is not set) will be generated.
In any sleeping state S1-M
wake event is generated.
has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit.
is detected by any of the PCI Requests being active, any internal bus master request being
active, the AGPBUSY# signal being active, or activity on any of the ICH4’s USB UHCI
Controllers. A USB Controller is considered active if all three of the following conditions are
true
This will occur every 2.3435 seconds. When the TMROF_EN bit is set, then the setting of the
TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN).
•The controller is not in Global Suspend
•At least one of the controller’s ports is not suspended
•3 The USB RUN bit is set
There are 3 USB UHCI controllers, each providing an independent signal into the BM_STS.
Bus Master IDE Controller activity will also cause BM_STS to be set. The ICH4’s BMIDE
Controller is considered active when the Controller’s Start bit is set.
AC’97 activity will also cause BM_STS bit to be set when any of the following conditions are
true:
•PICR.Run/Pause BM=1
•POCR. Run/Pause BM=1
•MCCR.Run/Pause BM=1
•MICR.Run/Pause BM=1
–
S5, while PWRBTN_EN and PWRBTN_STS are both set, a
Description
LPC Interface Bridge Registers (D31:F0)
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