FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 463

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.2.2.5
12.2.2.6
Intel
®
82801DBM ICH4-M Datasheet
CTRLDSSEGMENT—Control Data Structure Segment Register
Offset:
Default Value:
This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data
structures. Since the ICH4 hardwires the 64-bit Addressing Capability field in HCCPARAMS to
1s, then this register is used with the link pointers to construct 64-bit addresses to EHCI control
data structures. This register is concatenated with the link pointer from either the
PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a
64-bit address. This register allows the host software to locate all control data structures within the
same 4 GB memory segment.
PERIODICLISTBASE—Periodic Frame List Base Address Register
Offset:
Default Value:
This 32-bit register contains the beginning address of the Periodic Frame List in the system
memory. Since the ICH4 host controller operates in 64-bit mode (as indicated by the one in the
64-bit Addressing Capability field in the HCCSPARAMS register), then the most significant
32 bits of every control data structure address comes from the CTRLDSSEGMENT register. HCD
loads this register prior to starting the schedule execution by the Host Controller. The memory
structure referenced by this physical memory pointer is assumed to be 4-KB aligned. The contents
of this register are combined with the Frame Index Register (FRINDEX) to enable the Host
Controller to step through the Periodic Frame List in sequence.
31:12
31:12
11:0
11:0
Bit
Bit
Upper Address [63:44] — R/W. These bits are hardwired, read-only to 0 in the ICH4. The ICH4
EHC is only capable of generating addresses up to 16 terabytes (44 bits of address).
Upper Address [43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when forming a
control data structure address.
Base Address (Low) — R/W. These bits correspond to memory address signals [31:12],
respectively.
Reserved. Must be written as 0s. During runtime, the value of these bits are undefined.
CAPLENGTH + 10
00000000h
CAPLENGTH + 14
00000000h
–
–
13h
17h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W
32 bits
R/W
32 bits
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