FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 308

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.4
9.1.5
308
PCISTA—PCI Device Status (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
REVID—Revision ID Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
10:9
Bit
4:0
Bit
7:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = PERR# signal goes active. Set even if the PER bit is 0.
Signaled System Error (SSE) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = Set by the ICH4 if the SERR_EN bit is set and the ICH4 generates an SERR# on function 0. The
Master Abort Status (RMA) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = ICH4 generated a master abort on PCI due to LPC I/F master or DMA cycles.
Received Target Abort (RTA) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = ICH4 received a target abort during LPC I/F master or DMA cycles to PCI.
Signaled Target Abort (STA) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = ICH4 generated a target abort condition on PCI cycles claimed by the ICH4 for ICH4 internal
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = This bit is cleared by software writing a 1 to the bit position.
1 = Set when all three of the following conditions are true:
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. Indicates ICH4 as a target can accept
fast back-to-back transactions.
User Definable Features (UDF) — RO. Hardwired to 0
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0
Reserved
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
ERR_STS register can be read to determine the cause of the SERR#. The SERR# can be routed
to cause SMI#, NMI, or interrupt.
registers or for going to LPC I/F.
- The ICH4 is the initiator of the cycle,
- The ICH4 asserted PERR# (for reads) or observed PERR# (for writes), and
- The PER bit is set.
06
08h
0280h
No
See Bit Description
–
07h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/WC, RO
16 bit
Core
RO
8 bits