FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 285

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

7.2.10
Intel
®
82801DBM ICH4-M Datasheet
Power Management Driver (PMDR) Register
Offset Address:
Default Value:
The ICH4’s internal LAN Controller provides an indication in the PMDR that a wake-up event has
occurred.
4:1
Bit
7
6
5
0
Link Status Change Indication — R/WC.
0 = Software clears this bit by writing a 1 to the bit location
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable
Interesting Packet — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the
Reserved
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power Management
Control/Status Register (PMCSR).
0 = Software clears this bit by writing a 1 to the bit location. This also clears the PME Status bit in
1 = Set upon a wake-up event, independent of the PME Enable bit.
bit in the configuration command and the PME Enable bit in the Power Management Control/
Status Register.
LAN Controller packet filters.
the PMCSR and de-asserts the PME signal.
1Bh
00h
Description
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
R/WC
8 bits
285