FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 276

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.2
7.2.1
276
Table 7-4. Intel
LAN Control / Status Registers (CSR)
System Control Block Status Word Register
Offset Address:
Default Value:
The ICH4’s integrated LAN Controller places the status of its Command and Receive units and
interrupt indications in this register for the processor to read.
Bit
15
14
13
0Dh–0Ch
1Eh–3Ch
0Bh–08h
01h–00h
03h–02h
07h–04h
13h–10h
17h–14h
1A–19h
®
Offset
0Eh
1Bh
1Ch
1Dh
0Fh
18h
ICH4 Integrated LAN Controller CSR Space
Command Unit (CU) Executed (CX) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the CU has completed executing a command with its interrupt bit set.
Frame Received (FR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
CU Not Active (CNA) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = The Command Unit left the Active state or entered the Idle state. There are 2 distinct states of the
CU. When configured to generate CNA interrupt, the interrupt will be activated when the CU
leaves the Active state and enters either the Idle or the Suspended state. When configured to
generate CI interrupt, an interrupt will be generated only when the CU enters the Idle state.
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
Reserved
EEPROM Control Register
Reserved
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
Reserved
00
0000h
–
01h
Register Name
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
0000 0000h
0000 0000h
0000 0000h
0000 0000h
R/WC, RO
16 bits
Default
0000h
0000h
0000h
00h
00h
00h
N/A
00
—
—
—
R/W, RO, WO
R/W-Special
R/W-Special
R/WC
R/WC
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
—
—
—