FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 71
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
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Intel
®
Table 4-1. Intel
82801DBM ICH4-M Datasheet
Domains
Table 4-1
various system components, including the clock generator. For complete details of the system
clocking solution refer to the system’s clock generator component specification.
Intel
AC_BIT_CLK
System PCI
LAN_CLK
APICCLK
Domain
PCICLK
CLK66
CLK48
CLK14
Clock
ICH4
ICH4
ICH4
ICH4
ICH4
ICH4
®
ICH4-M and System Clock Domains
shows the system clock domains.
®
14.31818 MHz
12.288 MHz
5 to 50 MHz
Frequency
ICH4-M System Clock
66 MHz
33 MHz
33 MHz
48 MHz
33 MHz
AC ’97 Codec
LAN Connect
Component
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Generator
Generator
Generator
Generator
Generator
Generator
Source
Figure 4-1
Hub I/F, processor I/F. AGP. Shut off during S1-M or
below.
Free-running PCI Clock to ICH4. This clock remains on
during S0 state, and is expected to be shut off during S1-
M or below.
PCI Bus, LPC I/F. These only go to external PCI and LPC
devices. Will stop based on CLKRUN# (and STP_PCI#).
Super I/O, USB Controllers. Expected to be shut off
during S1-M or below.
Used for ACPI timer. Expected to be shut off during S1-M
or below.
AC’97 Link. Generated by AC ’97 Codec. Can be shut by
codec in D3. Expected to be shut off during S1-M or
below.
Used for ICH4-CPU interrupt messages. Runs up to
33 MHz. Expected to be shut off during S1-M or below.
Generated by the LAN Connect component. Expected to
be shut off during S1-M or below.
shows the assumed connection of the
Intel
®
ICH4-M System Clock Domains
Usage
71
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