FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 505

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

14.2.2
14.2.3
Intel
®
82801DBM ICH4-M Datasheet
x_CIV—Current Index Value Register
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32 bit read from address offset 04h. Software can also read this register individually by doing a
single 8 bit read to offset 04h. Reads across DWord boundaries are not supported.
x_LVI—Last Valid Index Register
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single
32-bit read from address offset 04h. Software can also read this register individually by doing a
single 8 bit read to offset 05h. Reads across DWord boundaries are not supported.
Bit
7:5
4:0
Bit
7:5
4:0
Hardwired to 0
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within the list of 32
descriptors is currently being processed. As each descriptor is processed, this value is
incremented. The value rolls over after it reaches 31.
Hardwired to 0.
Last Valid Index [4:0] — R/W. This field represents the last valid descriptor in the list. This value is
updated by the software each time it prepares a new buffer and adds it to the list.
NABMBAR + 04h (PICIV),
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
MBBAR + 44h (MC2CIV)
MBBAR + 54h (PI2CIV)
MBBAR + 64h (SPCIV)
00h
No
NABMBAR + 05h (PILVI),
NABMBAR + 15h (POLVI),
NABMBAR + 25h (MCLVI)
MBBAR + 45h (MC2LVI)
MBBAR + 55h (PI2LVI)
MBBAR + 65h (SPLVI)
00h
No
Description
Description
AC ’97 Audio Controller Registers (D31:F5)
Attribute:
Size:
Power Well:
Size:
Power Well:
Attribute:
RO
8 bits
Core
R/W
8 bits
Core
505