FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 289

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8
8.1
.
Intel
®
Table 8-1. Hub Interface PCI Configuration Register Address Map (HUB-PCI—D30:F0) (Sheet 1
82801DBM ICH4-M Datasheet
Note: Registers that are not shown should be treated as Reserved (see
Registers (D30:F0)
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH4 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
PCI Configuration Registers (D30:F0)
of 2)
Hub Interface to PCI Bridge
1E–1Fh
00–01h
02–03h
04–05h
06–07h
20–21h
22–23h
24–25h
26–27h
30–31h
32–33h
Offset
0Dh
1Ch
1Dh
08h
0Ah
0Bh
0Eh
18h
19h
1Ah
1Bh
PREF_MEM_BASE
PREF_MEM_MLT
SUB_BUS_NUM
PBUS_NUM
SBUS_NUM
IOBASE_HI
IOLIMIT_HI
Mnemonic
MEMBASE
HEADTYP
SECSTS
MEMLIM
PD_STS
IOBASE
REVID
IOLIM
PMLT
SMLT
CMD
SCC
BCC
DID
VID
Vendor ID
Device ID
PCI Device Command Register
PCI Device Status Register
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency Timer
IO Base Register
IO Limit Register
Secondary Status Register
Memory Base
Memory Limit
Prefetchable Memory Base
Prefetchable Memory Limit
I/O Base Upper 16 Bits
I/O Limit Upper 16 Bits
Register Name
Hub Interface to PCI Bridge Registers (D30:F0)
Section 6.2
See Note
Default
FFF0h
8086h
2448h
0001h
0080h
0280h
0000h
0000h
0000h
0000h
0000h
F0h
for details).
04h
06h
00h
01h
00h
00h
00h
00h
00h
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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