FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 429

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 11-3. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation
82801DBM ICH4-M Datasheet
When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1), the
single-stepping software debug operation is as follows:
To Enter Software Debug Mode:
1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to 0.
2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to 1.
SWDBG
Bit
(Bit 5)
1
0
0
0
1
1
Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers are slightly
different from Chip Hardware Reset and Global USB Reset. The HCRESET affects bits [8,3:0] of the
Port Status and Control Register (PORTSC) of each port. HCRESET resets the state machines of
the Host Controller including the Connect/Disconnect state machine (one for each port). When the
Connect/Disconnect state machine is reset, the output that signals connect/disconnect are negated
to 0, effectively signaling a disconnect, even if a device is attached to the port. This virtual
disconnect causes the port to be disabled. This disconnect and disabling of the port causes bit 1
(connect status change) and bit 3 (port enable/disable change) of the PORTSC to get set. The
disconnect also causes bit 8 of PORTSC to reset. About 64 bit times after HCRESET goes to 0, the
connect and low-speed detect will take place, and bits 0 and 8 of the PORTSC will change
accordingly.
0 = Reset by the Host Controller when the reset process is complete.
1 = Reset. When this bit is set, the Host Controller module resets its internal timers, counters, state
Run/Stop (RS) — R/W. When set to 1, the ICH4 proceeds with execution of the schedule. The ICH4
continues execution as long as this bit is set. When this bit is cleared, the ICH4 completes the
current transaction on the USB and then halts. The HC Halted bit in the status register indicates
when the Host Controller has finished the transaction and has entered the stopped state. The Host
Controller clears this bit when the following fatal errors occur: consistency check failure, PCI Bus
errors.
0 = Stop
1 = Run
NOTE: This bit should only be cleared if there are no active Transaction Descriptors in the
machines, etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated.
Run/Stop
(Bit 0)
executable schedule or software will reset the host controller prior to setting this bit again.
0
1
0
1
If executing a command, the Host Controller completes the command and then
stops. The 1.0 ms frame counter is reset and command list execution resumes
from start of frame using the frame list pointer selected by the current value in
the FRNUM register. (While Run/Stop=0, the FRNUM register can be
reprogrammed).
Execution of the command list resumes from Start Of Frame using the frame list
pointer selected by the current value in the FRNUM register. The Host Controller
remains running until the Run/Stop bit is cleared (by software or hardware).
If executing a command, the Host Controller completes the command and then
stops and the 1.0 ms frame counter is frozen at its current value. All status are
preserved. The Host Controller begins execution of the command list from
where it left off when the Run/Stop bit is set.
Execution of the command list resumes from where the previous execution
stopped. The Run/Stop bit is set to 0 by the Host Controller when a TD is being
fetched. This causes the Host Controller to stop again after the execution of the
TD (single step). When the Host Controller has completed execution, the HC
Halted bit in the Status Register is set.
Description
Description
USB UHCI Controllers Registers
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