FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 80

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.1.2
5.2.1.3
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The LAN Controller contains an interface to an external serial EEPROM. The EEPROM is used to
store relevant information for a LAN connection such as node address, as well as board
manufacturing and configuration information. Both read and write accesses to the EEPROM are
supported by the LAN Controller. Information on the EEPROM interface is detailed in
Section
FIFO Subsystem Overview
The ICH4 LAN Controller FIFO subsystem consists of a 3-kB transmit FIFO and 3-KB receive
FIFO. Each FIFO is unidirectional and independent of the other. The FIFO subsystem serves as the
interface between the LAN Controller parallel side and the serial CSMA/CD unit. It provides a
temporary buffer storage area for frames as they are either being received or transmitted by the
LAN Controller, which improves performance:
Serial CSMA/CD Unit Overview
The CSMA/CD unit of the ICH4 LAN Controller allows it to be connected to the 82562ET/EM
10/100 Mbps Ethernet LAN Connect components. The CSMA/CD unit performs all of the
functions of the 802.3 protocol (e.g., frame formatting, frame stripping, collision handling, deferral
to link traffic, etc.). The CSMA/CD unit can also be placed in a full-duplex mode, which allows
simultaneous transmission and reception of frames.
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Transmit frames can be queued within the transmit FIFO, allowing back-to-back transmission
within the minimum Interframe Spacing (IFS).
The storage area in the FIFO allows the LAN Controller to withstand long PCI bus latencies
without losing incoming data or corrupting outgoing data.
The ICH4 LAN Controller’s transmit FIFO threshold allows the transmit start threshold to be
tuned to eliminate underruns while concurrent transmits are being performed.
The FIFO subsection allows extended PCI zero wait-state burst accesses to or from the LAN
Controller for both transmit and receive frames since the transfer is to the FIFO storage area
rather than directly to the serial link.
Transmissions resulting in errors (collision detection or data underrun) are retransmitted
directly from the LAN Controller’s FIFO, increasing performance and eliminating the need to
re-access this data from the host system.
Incoming runt receive frames (in other words, frames that are less than the legal minimum
frame size) can be discarded automatically by the LAN Controller without transferring this
faulty data to the host system.
5.2.3.
Intel
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82801DBM ICH4-M Datasheet